1. Field of the Invention
The present invention generally relates to the field of semiconductor technology, and more particularly to a semiconductor device and a manufacturing method thereof.
2. Description of the Prior Art
A flash memory is a non-volatile memory, which can preserve data within the memory even when an external power supply is off. Recently, since flash memories are re-writable and re-erasable, they have been widely utilized in the fabrication of electrical products, such as mobile phones, digital cameras, video players, personal digital assistants (PDA) or systems on a chip (SOC).
Please refer to FIG. 1, which is a cross sectional diagram illustrating a conventional flash memory cell. As shown in FIG. 1, a flash memory cell 10 includes a semiconductor substrate 60, two stack gates 12, two select gates 20a/20b and an erase gate 22. Both of the stack gates 12 are disposed on the semiconductor substrate 12. The select gates 20a/20b are respectively disposed at one side of the stack gates 12, while the erase gate 22 is disposed between the two adjacent stack gates 12. More precisely, each of the stack gates 12 includes at least a floating gate 16 and a control gate 18 stacked from bottom to top. The floating gate 16, the control gate 18 and the select gate 20a/20b are commonly made of polysilicon, and dielectric layers 24/26/28 such as oxide layers may be respectively disposed between the two adjacent gates for electrical insulation. The dielectric layers 24 disposed between the floating gate 16 and the semiconductor substrate 60 may serve as a tunneling oxide, through which the hot electrons may get in or out of, thereby achieving data accessing. The flash memory cell 10 may further include source/drain regions 30/32/34 disposed in the semiconductor substrate 60 at two sides of the stack gates 12, and include channel regions (not shown) defined in the semiconductor substrate 60 between the two adjacent source/drain regions 30/32/34. When the flash memory cell 10 is operating, portions of the electrons moving in the channel regions may be injected into the floating gate 16 by applying suitable positive voltage to the control gate 18 thereby achieving data accessing.
In the manufacturing process for the conventional flash memory cell 10, a conductive material made of polysilicon (not shown) is usually deposited on the semiconductor substrate 60 to completely cover the stack gates 12 and the space therebetween. Afterwards, a planarization and an etching back process may be carried out to remove upper portions of the conductive material and expose the stack gates 12. In a next step, a photolithographic process and an etching process may be performed to pattern the remaining conductive material. As a result, a main structure of the conventional flash memory cell 10 is obtained. In this structure, the conductive material on the inner sides of the stack gates 12 (i.e. between the two stack gates) may serve as an erase gate 22, while the conductive material outside the stack gates 12 may serve as select gates 20a/20b. 
However, with the continuous reduction in the size of the conventional flash memory cells, even though the conductive material is planarized through the above-mentioned planarization process, the thickness of the conductive material within different regions is still uneven. Besides, the etching back process often damages the dielectric layer 28 on the side surfaces of the control gate 18 and degrades the performance of the flash memory cell 10. Furthermore, since a misalignment often occurs during the photolithographic process, this phenomenon causes a large variation in the width W1/W2 of the select gates 20a/20b and further influences the channel length underneath the select gates 20a/20b. Such variation in the channel length under the erase gates 20a/20b reduces the reliability of the flash memory cell 10. Consequently, how to avoid the variation in the erase gates is still an important issue in the field, in order to improve the performances of the flash memory cell.